The present invention generally relates to an isolation structure for semiconductor devices, and more particularly relates to a shallow-trench isolation (STI) structure.
As semiconductor technologies evolve, some conventional approaches for forming quarter (0.25) micron and smaller features become more problematic. One such example is local oxidation of silicon (LOCOS) for forming field oxide regions in an array of memory integrated circuit cells. In LOCOS, a nitride hard mask is patterned to cover designated active areas on a silicon substrate. During LOCOS oxidation of exposed field regions of the silicon substrate, the nitride hard mask deflects upwardly at the interface of field regions and active areas owing to encroachment of the LOCOS under the mask (i.e., encroachment into the active areas). Additionally, LOCOS formation is inherently non-planar, which makes it relatively difficult for use in 0.25 micron or smaller geometries in large-scale integration for isolating one device from another.
Consequently, shallow-trench isolation (STI) has been suggested as a practical alternative to LOCOS for 0.25 micron and smaller topographies. With STI, a more planar structure may be achieved, especially when compared with semi-recessed LOCOS. For example, an STI structure may be planarized by subsequent etch back or chemical-mechanical polishing (CMP) to form an optimally planar surface.
A problem with STI is that a recess in an STI field oxide near an active area edge causes sub-threshold voltage conduction (leakage current) across a metal-oxide-semiconductor-field-effect-transistor (MOSFET) adjacent to a defective STI structure. It is believed that the field oxide recess causes field crowding at the active area edge of the trench leading to sub-threshold conduction. Such a recess may be caused by over polishing during CMP or deglazing.
To address this problem, others have suggested that a gate oxide be grown prior to forming an STI trench. The formed trench is then filled with an oxide. A CMP step is employed to form a surface of the field oxide planar to the deposited gate oxide (ie., above the silicon wafer surface). Accordingly, this process avoids a field oxide recess near a gate edge and a field edge of an adjacent transistor. However, this process necessitates forming a gate oxide early, which is then subjected to subsequent processing steps which may adversely impact the quality or the integrity of the gate oxide.
Accordingly, it would be desirable to provide an STI structure that provides less probability of leakage current. Moreover, it would be desirable to provide a process which reduces probability of subthreshold voltage transistor leakage, but which also allows for gate formation later in the process.
The present invention provides structure for isolating one integrated circuit from another and method for forming an isolation structure. More particularly, an STI structure in accordance with the present invention may be employed for electrically isolating a plurality of devices in an integrated circuit from one another.
In accordance with the present invention, a base material member, such as a semiconductor substrate, has one or more recesses formed about a surface of the member. Pitch or spacing of these recesses may be determined at least in part by circuit requirements and process equipment limitations. An oxide layer is formed in the recesses. The oxide layer may be formed by one or more sub-layers, and may be formed by high-pressure oxidation (HIPOX) or by thermal oxidation. Notably, use of HIPOX facilitates oxidation more readily along the bottom, as opposed to the sidewalls, of a recess, and thus aspect ratio is improve for any subsequent deposition to fill the recess.
In the HIPOX embodiment, impurities (e.g., dopants) may be implanted in the semiconductor substrate at the bottom of the recess prior to formation of the oxide layer. This implanting may be used to aid subsequent oxidation. In the HIPOX embodiment, nitrogen may be flowed into a HIPOX chamber to form at least a part of the oxide layer. Any remaining vacancies in the recesses may be filled with a dielectric material.
The dielectric material may be deposited, for example, as a layer over the base member. An unwanted portion of the dielectric material may be removed by etching or by polishing. A portion of the dielectric material may be provided to and remain on an upper surface of the base member to provide a dielectric layer for forming a portion of an integrated circuit device, such as a gate oxide for a transistor or a dielectric for a capacitor.
It is a desired goal that the present invention provide improved isolation by providing a sub-liner layer of a high quality oxide.